In the art of complementary MOS semiconductor device (hereinafter referred to as CMOS) comprising p-channel and n-channel transistors, it has been increasingly demanded to establish a fine topographic technology with the need for high density and high integration while making the use of an advantage of small power consumption.
With regard to the structure of CMOS, a bipolar parasitic transistor circuit is arranged in the internal part in the same arrangement as thyrister. As a result, a problem exists in that when triggered by surge or the like from outside, an excessively large current may flow from power terminal to ground terminal causing thereby a phenomenon of latchup in which current still continues to flow even after disappearance of surge or the like, eventually resulting in breakdown of the device due to such large current. Under such circumstances, it may be said that a novel structure of CMOS is essential from the viewpoint of improvement of resistance to latchup, though requirements of the resistance will be more strict under the recent need for finer topography. Among several proposals ant attempts, retrograde well structure is known. FIG. 11 is a structural sectional view and circuit diagram schematically illustrating a structure of a CMOS inverter arranged in the simplest manner and a parasitic thyrister equivalent circuit.
In FIG. 11, reference numeral (1) indicates a p-type silicon semiconductor substrate of 1.times.10.sup.15 cm.sup.-3 in concentration and 10 .OMEGA..multidot.cm in resistivity; numeral (2) indicates a field oxide film which is formed on one main surface of the mentioned p-type semiconductor substrate (1) and serving as a device separating region; numeral (3) indicates a n-well region which is formed by carrying out first implantation of phosphorus ion into an island-shaped region formed being separated by the mentioned field oxide film (2) on condition of 700 kev in acceleration voltage and 1.times.10.sup.13 cm in dose, and second implantation of phosphorus ion on condition of 200 kev in acceleration voltage and 1.times.10.sup.12 cm.sup.-2 in dose; numeral (4) indicates a bottom part of higher impurity concentration (1.times.10.sup.16 to 1.times.10.sup.17 cm.sup.-3) in the mentioned n-well region (3); numeral (5) indicates a p-well region which is formed by carrying out first implantation of boron ion into a region adjacent the mentioned island-shaped n-well region (3) formed being separated by the mentioned field oxide film (2) on condition of 400 kev in acceleration voltage and 1.times.10.sup.13 cm.sup.-2 in dose, and second implantation of boron ion on condition of 100 kev in acceleration voltage and 1.times.10.sup.12 cm.sup.-2 in dose; numeral (6) indicates a bottom part of higher impurity concentration (1.times.10.sup.16 to 1.times.10.sup.17 cm.sup.-3) in the mentioned p-well region (5); numeral (7) indicates a n.sup.+ -type well contact region for supplying potential to the mentioned n-well region (3); numeral (8) indicates a p.sup.+ -type well contact region for supplying potential to the mentioned p-well region (5); numeral (9a) indicates a p.sup.+ -type source region arranged in the mentioned n-well region (3) to form a p-channel transistor of the CMOS inverter; numeral (9b) indicates a p.sup.+ -type drain region arranged in the mentioned n-well region (3) to form a p-channel transistor of the CMOS inverter together with the mentioned p.sup.+ -type source region (9a); numeral (10a) indicates a n.sup.+ -type source region arranged in the mentioned p-well region (5) to form a n-channel transistor of the CMOS inverter; numeral (10b) indicates a n.sup.+ -type drain region arranged in the mentioned p-well region (5) to form a n-channel transistor of the CMOS inverter together with the mentioned n.sup.+ -type source region (10a); numeral (11a) indicates a gate electrode of the p-channel transistor of the CMOS inverter; numeral (11b) indicates a gate electrode of the n-channel transistor of the CMOS inverter; numeral (12) indicates a parasitic PNP transistor in which said p.sup.+ -source region (9a) is an emitter, said n-well region (3) is a base, and said p-type silicon semiconductor substrate (1) is a collector; numeral (13) indicates a parasitic NPN transistor in which said n.sup.+ -source region (10a) is an emitter, said p-well region (5) is a base, and said p-type silicon semiconductor substrate (1) is a collector, said parsitic NPN transistor (13) forming a parasitic thyrister together with the mentioned parasitic PNP transistor (12). In addition, numeral (14) indicates a parasitic resistance of the mentioned n-well region (3), and numeral (15) is a parasitic resistance of the mentioned p-well region (5).
In the conventional CMOS of above arrangement, the parasitic resistance (14) drops due to formation of the bottom part (4) of high impurity concentration in the n-well region (3), thereby the parasitic PNP transistor (12) becomes difficult to turn on because of reduction in potential difference between the base and emitter. Furthermore, because of increase in concentration of a region corresponding to the base of the parasitic PNP transistor (12), recombination takes place frequently at the base, thus current amplification factor of the parasitic PNP transistor (12) being reduced.
Meanwhile, the parasitic resistance (15) drops due to formation of the bottom part (6) of high impurity concentration in the p-well region (5), thus the parasitic NPN transistor (13) becomes difficult to turn on because of reduction in potential difference between the base and emitter. Moreover, because of increase in concentration of a region corresponding to the base of the parasitic NPN transistor (13), recombination takes place frequently at the base, thus current amplification factor of the parasitic NPN transistor (13) is reduced.
Accordingly, loop gain of the parasitic thyrister formed of the parasitic PNP transistor (12) and the parasitic NPN transistor (13) is restricted, thereby resistance to latch-up being enhanced.
It is generally recognized that resistance to latchup of the conventional CMOS of above structure is intensified by 2 to 3 times as compared with the one having a bottom part without high impurity concentration, depending upon the distance between the n.sup.+ -type source region (10a) corresponding to width of the base of the parasitic NPN transitor (13) and the n-well region (3).
It is, however, sometimes the case that when receiving a noise of backward component among noises of electronic apparatus generated outside the semiconductor chip and applying a voltage lower than ground potential (GND) to the n.sup.+ -type drain region (10b), electrons are delivered to the p-type silicon semiconductor substrate (1) through the p-well region (5), and a part of the electrons is collected in the n-well region (3) corresponding to the collector region of the parasitic NPN transistor (13), then comes to the n.sup.+ -type well contact region (7) passing through the n-well region (3). As a result, a voltage drop occurs thereby p-n junction between the p.sup.+ -source region (9a) and n-well region (3) being forward biased, and the parasitic PNP transistor (12) is turned on, permitting flow of collector current.
If this current is so large as to cause the p-n junction between the n.sup.+ -drain region (10a) and p-well region (5) to be forward biased due to voltage drop by the parasitic resistance (15), then the parasitic NPN transistor (13) is turned on and collector current is generated, which brings about more intensive conduction state of the parasitic PNP transistor (12).
In such a state as positive feedback is applied in the mentioned manner, a problem exists in that a large current is left free to flow between V cc and GND irrespective of the current from the n.sup.+ -type drain region (10b) serving as a first trigger, eventually resulting in thermal breakdown of the chip itself.
The present invention was made to solve the above problems and has an object of providing a CMOS of which resistance to latchup is sufficiently improved.